• 专利附录
  • 专利说明
  • 权利要求
  • 类似技术
  • 同族专利
  • 引用文献
  • 法律状态
  • 优先权
    • 专利摘要:
    A license verification circuit for selectively activating one or more protected circuits (206) of a device (102), wherein the license verification circuit is adapted to: derive a device key from an identifier associated with the device (102); receive a first license; decrypting the first license using the device key to retrieve a first verification code; activate a first protected circuit by loading an activation code into an activation register (212) associated with the first protected circuit on the basis of a verification of the first verification code.
    公开号:FR3038757A1
    申请号:FR1556418
    申请日:2015-07-07
    公开日:2017-01-13
    发明作者:Lionel Torres；Jerome Rampon；Gael Paul
    申请人:Centre National de la Recherche Scientifique CNRS；Universite de Montpellier I；Universite de Montpellier；
    IPC主号:
    专利说明:

    SYSTEM AND METHOD FOR AUTHENTICATION AND IP LICENSE
    Field
    The present disclosure relates to the field of integrated circuits and in particular a method and a system for authenticating and issuing licenses for blocks of intellectual property (IP) in an integrated circuit, and more generally authentication and attribution. licenses for all circuits or systems.
    Presentation of the prior art
    Integrated circuits generally include a number of circuit blocks known in the art as Intellectual Property (IP) blocks. IP blocks are designs of discrete hardware circuits that perform specific functions and can be reused in a variety of different integrated circuits. IP blocks in a given integrated circuit (IC) are typically licensed to an IC designer by IP block rights owners.
    IP blocks are generally provided to the designer of integrated circuits as software, for example in a hardware description language such as Register Transfer Level (RTL), Verilog or Very High speed integrated circuit hardware (VHDL). Description Language - hardware description language of very high speed integrated circuits. IP assigns often license the IC designer to use their IP block in a limited number of integrated circuits and / or a limited number of projects, or claim royalties for each integrated circuit / project that integrates IP block. However, piracy of integrated circuits has become an increasingly important problem. Indeed, from the moment when the IP block is delivered to the designer of integrated circuits, it is very difficult for the IP rights-holders to control the way their IP block is used, and to limit the number of integrated circuits manufactured in using their design.
    Some solutions have been proposed to allow IP rights holders to lock their circuit designs. However, existing solutions tend to be complex, expensive and / or not sufficiently secure. summary
    An object of embodiments of the present disclosure is to at least partially solve one or more needs of the prior art.
    In one aspect, there is provided a license verification circuit for selectively activating one or more protected circuits of a device, wherein the license verification circuit is adapted to: derive a device key from an identifier associated with the device; receive a first license; decrypting the first license using the device key to retrieve a first verification code; activate a first protected circuit by loading an activation code into an activation register associated with the first protected circuit based on a verification of the first verification code.
    In one embodiment, the identifier associated with the device is provided to a physically unclonable function, PUF ·.
    According to one embodiment, the license verification circuit is adapted to read the identifier associated with the device on an interface protected by encryption.
    According to one embodiment, the license verification circuit further comprises: a license server comprising a key deduction circuit for deriving the device key and a decryption circuit for decrypting the first license; a first license client associated with the first protected circuit and including a first control circuit for activating the first protected circuit based on the first verification code; and a second license client associated with a second protected circuit and including a second control circuit adapted to activate the second protected circuit by loading a second activation code into an activation register associated with the second protected circuit.
    In one embodiment, the license server is adapted to transmit the first verification code to the first license client and the second verification code to the second license client.
    According to one embodiment, the first verification code is encrypted by the license server on the basis of another key extracted from the first license and transmitted to the first control circuit of the first license client.
    According to one embodiment, the decryption circuit is further adapted to extract the other key from the first license.
    According to one embodiment, the first verification code comprises the activation code encrypted using an IP vendor key, the first license client being further adapted to store the IP vendor key in a memory and to decrypt the first code verification on the basis of the IP vendor key to retrieve the activation code.
    According to one embodiment, the first license client comprises: an interrogation generation circuit comprising a random number generator adapted to generate an interrogation value and to transmit the interrogation value to the license server; and a first response generation circuit adapted to generate a first response value based on at least the interrogation value, the license server comprising: a second response generation circuit adapted to receive the interrogation value and generating a second response value based on at least the interrogation value, the first license client further comprising a verification circuit adapted to compare a first response value with the second response value.
    In one embodiment, the first and second response generation circuits are adapted to generate the first and second response values based on a hash function.
    According to one embodiment, the first license client comprises a non-volatile memory storing a copy of the activation code, the first control circuit being adapted to load the copy of the activation code in the activation register on the basis of a verification of one or more values of the first verification code.
    According to one embodiment, the verification code comprises other data indicating one or more of the following elements: a period of validity of the license; a geographical limit of the license; a limitation of the license to one or more types of equipment; a temperature limitation of the license; a voltage limitation of the license; bandwidth limitation of the license; a speed limitation of the license; an acceleration limitation of the license; a humidity limitation of the license; a light level limitation of the license; a magnetic field limitation of the license; and a radioactivity limitation of the license.
    According to one embodiment, the first activation code comprises a plurality of bits, and the first protected circuit comprises a plurality of logic gates adapted to selectively activate a signal path of the first protected circuit, each logic gate having a first input coupled to a node of the first protected circuit and a second input coupled to receive one of the bits stored by the activation register.
    In another aspect, there is provided a license verification system comprising: a first IP (proprietary) module comprising the aforementioned license verification circuit; a second IP module including the aforementioned license checking circuit; and a circulator adapted to transmit the first license to the first IP module and a second license to the second IP module.
    In another aspect, there is provided a license generation circuit comprising: a key deduction circuit adapted to derive a device key based on a device identifier of a device; an encryption circuit adapted to generate a first license for one or more protected circuits of the device by encrypting one or more activation codes using the device key.
    According to one embodiment, the encryption circuit is further adapted to encrypt another key to be included in the first license.
    In yet another aspect, there is provided a license verification method for selectively activating one or more protected circuits of a device, the method comprising: deriving a device key from an identifier associated with the device; receive a first license; decrypting the first license using the device key to retrieve a first verification code; and activate a first protected circuit by loading the first activation code into an activation register associated with the first protected circuit based on a verification of the first verification code.
    Brief description of the drawings
    The aforementioned and other advantages will become apparent from the following detailed description of embodiments, given by way of illustration and not limitation, with reference to the accompanying drawings, in which: Figure 1A schematically illustrates a system for licensing IP blocks according to an exemplary embodiment of the present description; Fig. 1B illustrates a license generation circuit of Fig. 1A in more detail according to an exemplary embodiment; FIG. 2 diagrammatically illustrates an integrated circuit comprising components for issuing an IP license according to an exemplary embodiment of the present description; FIGS. 3A and 3B schematically illustrate activation circuits of an IP block according to an exemplary embodiment of the present description; FIG. 4 schematically illustrates a license server and a license client of the integrated circuit of FIG. 2 in greater detail according to an exemplary embodiment of the present description; Fig. 5 is a flowchart illustrating operations in a method of activating an IP block on a license basis using the license server and the license client of Fig. 4 according to an exemplary embodiment of the present invention. description; FIG. 6 schematically illustrates a license server and a license client of the integrated circuit of FIG. 2 in more detail according to another example of the present description; Fig. 7 is a flowchart illustrating operations in a method of activating an IP block based on a license using the license server and the license client of Fig. 6 according to another embodiment of the present invention. present description; FIG. 8 schematically illustrates a secure interface between a license client and a license server of FIG. 2 in more detail according to another embodiment of the present description; FIG. 9 schematically illustrates components for issuing a license on an integrated circuit according to yet another embodiment of the present description; FIG. 10 schematically illustrates components for issuing a license on an integrated circuit according to yet another embodiment of the present description; Figs. 11A and 11B are map level views schematically illustrating components for issuing a license according to an embodiment of the present disclosure; and Fig. 12 schematically illustrates an FPGA (Field Programmable Gate System) comprising components for issuing a license according to an exemplary embodiment of the present disclosure.
    detailed description
    Although in the description which follows the embodiments are described in a hardware implementation, it will be apparent to one skilled in the art that the various embodiments could be at least partially implemented by software instructions. executed by one or more processors.
    In the following description, the following terms will be given the following definitions: IP block - discrete hardware circuit design that performs specific functions and can be reused in various different integrated circuits; circuit-protected circuit, which may be an IP block, a certain number of IP blocks or a system comprising one or more integrated circuits, protected by a mechanism as it is in a disabled state, unless be activated by an activation code.
    FIG. 1A schematically illustrates a system 100 for authenticating and issuing licenses for protected circuits according to an exemplary embodiment of the present description.
    The system 100 includes hardware associated with three main partners, an IP seller, IP (IP VENDOR), a trusted third party (TTP), and an end user (END USER). Protection is based on a unitary activation of one or more protected circuits. Each protected circuit is for example a complex circuit developed to perform a specific function, such as an interface for managing standard protocols, a circuit capable of performing advanced operations, such as a processor, a coding or decoding circuit, etc. The protected circuits are for example implemented using one or more specific application circuits and / or using one or more field programmable gate networks (FPGAs).
    In the example of FIG. 1A, it is assumed that a circuit 102, bought or otherwise obtained by the end user, comprises one or more protected circuits 103. In the example of FIG. 102 is an integrated circuit, and the protected circuits 103 are IP blocks of the integrated circuit. However, in alternative embodiments, the device could correspond to any electronic device, and the protected circuits could each comprise a card or a system having more than one integrated circuit.
    The integrated circuit 102 is for example part of a product such as a mobile phone, a tablet computer, a laptop, a game console or the like, or could be a chip mounted on an integrated circuit card, this including the family of cards known as smart cards, including for example payment cards, SIM cards (subscriber identity module) or the like.
    According to the embodiments described here, said one or more IP blocks 103 on the integrated circuit 102 are for example in a deactivated state when the end user receives the integrated circuit 102, and the end user activates the disabled IP blocks by requesting a license from the IP vendor or the TTP. However, in alternative embodiments, rather than being performed by the end user, the activation may be performed by another partner in the supply chain, such as the designer of the integrated circuit, or a seller of a product. containing the integrated circuit 102.
    The device 102 comprises, for example, a device identifier (DEVICE ID), which comprises a bit string which identifies the device 102 or a group of devices 102, and which serves, for example, for authentication. The license that is provided by the IP vendor or the TTP can only be used for a device with this identifier, and in some embodiments, the device identifier is unique for each device, so that a given license can only However, it would also be possible in some embodiments to provide a single license that activates a set of devices, which for example have the same device identifier. The device identifier is for example generated by or deduced from a physically unclonable function, PUF. The activation of one or more of the protected circuits of the device 102 may be permanent, which means that once activated the protected circuits of the device 102 will remain activated. In addition to or instead, one or more of the protected circuits could remain enabled until a subsequent reset operation of the device 102, and at this point a license might be needed again to reactivate these protected circuits. The license may remain stored on the device, and so during a power up sequence, a pre-initialization operation (an operation before the reset signal is disabled) involves loading the license, which is already stored in a memory , in the chip to activate one or more of the protected circuits.
    In addition to or instead, the license may initially activate one or more of the protected circuits for a limited time or for a given number of clock cycles of a device clock. For example, it allows to have a demonstration mode during a temporary period, in which all or only some of the protected circuits are active, and at the end of the temporary period, a complete license is for example necessary to activate the circuits protected.
    As will become clear with the following description, the particular type of activation (permanent, until a next reset, or temporary) may be different for each protected circuit of the device. Furthermore, although the method described here can be used to activate a single IP block, it can also be applied more generally to the activation of any protected circuit which can correspond to all the IP blocks of a device. given, to an IP block in another IP block and / or to an IP block comprising another IP block, to a system or a smart card, to the activation of all the circuits in a design using ASIC technology (application specific integrated circuit) given, upon activation of a given family of FPGAs, the activation of FPGAs produced by a given manufacturer, etc. It could also be applied at the system level. In addition, in some embodiments, the license may be used to activate or deactivate only a subset of the functions of an IP block. "
    As will be described in more detail below, the method and device described herein also allow for example a protected circuit, or a sub-function, of a protected circuit to be activated and deactivated several times.
    An example of the process to protect and activate an IP block will now be described in more detail. Although this example is based on the protection of an IP block, as mentioned previously, in alternative embodiments, it could be applied to the protection of other types of circuits.
    At the IP vendor level, a database (RTL) 104 stores for example one or more IP blocks represented in a hardware description language such as ordinary RTL code (register transfer level).
    An IP Protector block 106 includes, for example, software for performing an IP protection function, which is used to modify one or more of the IP blocks from the database 104 to render the circuit inactive. In particular, the IP block is altered so that an activation code is needed to unlock its features. In some embodiments, this step can be performed entirely automatically, although in other embodiments it can be performed at least partially manually, for example by a designer of the IP block. As will be described in more detail below, the modification of the IP block involves for example the insertion, in the hardware description file, of one or more logic gates in one or more signal paths of the IP block. These logic gates allow for example the propagation of the unaltered signal in the signal path only if one or more correct activation bits are provided to one or more input nodes of the logic gates inserted. In some embodiments, the activation code may be unique for a given IP design. In other embodiments, the same activation code may be used for multiple IP designs. In addition, in some embodiments, there may be more than one activation code that can activate an IP block. This can for example facilitate the licensing operation.
    A circuit for managing the IP license, which will be called here license client (not shown in Figure IA) is for example added to each IP block to protect. As will be described in more detail below, the license client includes, for example, a register for storing the activation code once a valid license has been provided. In some embodiments, the license client is integrated into each IP block, although as described in more detail below, each license client could also be outside the corresponding IP block.
    In some embodiments, the files representing the modified IP blocks are for example also protected by encryption.
    The activation codes, and optionally some or all of the modified IP blocks, are for example stored in a database (PROTECTED IP) 108 of the IP vendor. The modified IP blocks are also provided to a designer of the integrated circuit 102 so that, as represented by an arrow 110 in FIG. 1A, one or more protected IP blocks 103 are implemented as hardware in the integrated circuit. In particular, the designer of the integrated circuit for example combines various IP blocks to form an integrated circuit, and a plurality of these IP blocks correspond for example to IP blocks protected by an activation code as described here.
    The license includes for example a verification code. The term "verification code" is used here to refer to a code that is communicated with the license and allows one or more IP blocks to be activated. This code can be the activation code for one or more IP blocks. In alternative embodiments the activation code is already stored in a protected memory, for example a ROM, of the IP block, and the activation code is not included in the license. In this case, the verification code is a secret code communicated with the license to the IP block and which allows the activation code to be loaded from the protected memory into the activation code register. In some embodiments, a temporary license may be provided to the IC designer for the purpose of circuit design or testing.
    The integrated circuit designer also includes for example a license server (LICENSE SERVER) 114 in the integrated circuit 102. This circuit is for example provided by the TPP, or it can be integrated in one or more of the IP blocks protected by the seller. IP. The license server 114 is for example coupled to a port of the integrated circuit through which the license can be received. The license server 114 is also for example coupled to each protected IP block of the integrated circuit, and in particular to the license client circuit of each IP block.
    The license server 114 also includes for example a circuit for generating the device identifier, for example in the form of a PUF. As will be described in more detail below, the device identifier is for example based on the generation of a signature that is unique to the integrated circuit. Therefore, even if two integrated circuits are manufactured and / or programmed to have identical functionalities, their signatures and therefore their device identifiers will be different. The value PUF is for example generated by a CPU (central processing unit) of the integrated circuit, and / or is based on one or more ring oscillators mounted on the integrated circuit. PUFs are for example described in more detail in the following publications: the publication of David Naccache et al. entitled "Unforgeable identification device, identification device reader and method of identification", August 1992; G. Simmons' publication "Identification of data, devices, documents and individuals", IEEE International Carnahan Conference on Security Technology, 1991, pp. 197-218; the publication of Stefan Katzenbeisser et al. entitled "PUFs: Myth, Fact or Busted A Security Evaluation of Physically Unclonable Functions (PUFs)
    Cast in Silicon ", (2012), Hardware and Embedded Systems Cryptography - CHES 2012. 14th International Workshop, Leuven, Belgium, 9-12 September, 2012. Proceeding, Lecture Notes in Computer Science 7428, Heidelberg Springer Berlin, pages 283-301 , doi: 10.1007 / 978-3-642-33027-8_17, ISBN 978-3-642-33026-1, the publication of Roel Maes et al entitled "Physically Unclonable Functions: A Study on the State of the Art and Future". Research Directions "L. Bossuet et al., Entitled" A PUF based on a transient ring oscillator and insensitive to locking phenomenon ", IEEE Transactions on Emerging Topics in Computing, Vol 2, Issue 1, pages 30-36. , 2014, the publication of P. Bayon et al., Entitled "EM radiation analysis on the true random number generators: Frequency and localization retrieval method", APEMC, 2013, the publication of Z. Cherif et al entitled "A easy-to- PUF, "DSD, 2012, the publication of B. Gassend et al. ntitled "Silicon Physical Random Functions", ACM CCS, pages 148-160, 2002; the publication of J. Guajardo et al. entitled "FPGA Intrinsic PUFs and Their Use for IP Protection," CHES, Springer, LNCS, vol. 4727, pp. 63-80, 2007; D. Merli's publication "Semi-invasive EM attack on FPGA RO PUFs and Countermeasures" ACM WESS, 2011; and the publication of G. E. Suh et al. The contents of these eleven publications are considered included herein to the extent permitted by law. "Physical unclassifiable functions for device authentication and secret key generation," DAC.
    When the integrated circuit is activated for the first time after its manufacture and / or programming, the value of the device identifier is read for example by reading a value generated by a PUF circuit or the like. In some cases, the PUF value may change over time due to the aging of the integrated circuit, and / or for other reasons such as the environment (temperature, voltage, etc.). In some embodiments, in view of a potential change in the PUF, at least a portion of the generated PUF value is stored in a nonvolatile memory, and / or an error correction code is generated, which allows the PUF value to be corrected if some bits of the PUF value deviate from their original value. The device identifier is also provided at an access port of the integrated circuit 102, or otherwise communicated outside of the integrated circuit 102, and is used to request a license to activate the devices. protected IP blocks.
    As an alternative to a PUF, another form of device identifier could be used, such as an identifier assigned to the device by the device manufacturer.
    The license generation is for example performed by the IP vendor, or by the trusted partner, in response to a request from the end user or another partner wishing to activate an integrated circuit 102. The license request includes 1 device identifier, which is read in the integrated circuit 102.
    In one example, the activation request may include a request for the activation of multiple IPs. For example, an application may be provided, for example on an external computer coupled to the integrated circuit, which interacts with the integrated circuit 102 to obtain the device identifier. The device identifier is then transmitted to a license server (LICENSE SERVER) 126 of the trusted partner. The license server 126, for example, in turn distributes license requests to each of the IP sellers of the IP modules of the integrated circuit. A customer relationship management application located at the IP vendor, for example, consults a customer database and verifies that the license can be provided. For example, it verifies that the integrated circuit having the corresponding device identifier is not a stolen circuit, and that the. payment for the license has been received. The IP seller then generates, for example, a license based on the device identifier, and transmits the license to the license server 126 of the TTP, where the license is for example stored and transmitted to the integrated circuit 102 for use in the. activation process.
    Of course, many variations could be applied to this procedure. For example, a customer database may be stored at the TTP level, along with a license generating circuit for generating a license to activate one or more IP blocks of an integrated circuit based on the identifier of device.
    In some embodiments, a separate license is generated for each IP block to be activated. Alternatively, a license may be generated to activate a plurality of IP blocks. For example, the license includes the verification code of each IP block to be activated.
    In the case where the license is generated by the IP seller, the code or the verification codes (CHECK CODE) 115 necessary to unlock the protected IP block (s) of the integrated circuit 102 are for example supplied to a license generator (LICENSE GENERATOR ) 116 at the IP vendor level. The license generator 116 is used to generate a license (LICENSE) which is for example transmitted to the license server 114 of the integrated circuit 102. The license generator 116 receives for example the device identifier (DEVICE ID) from the circuit integrated 102, and generates the license based on this identifier and the verification code (s). In some embodiments, the license also integrates DRM (Design Rights Management) data 120. The DRM data indicate for example a limit in the duration of activation of an IP block, for example in the case where the license is a temporary license. They may also indicate a limitation of the license to one or more types of hardware, such as ASIC technology, an FPGA family, or specific features of an IP block that need to be unlocked. The type of hardware of the circuit may for example be determined by a specific sensor, and be compared to said one or more types of authorized hardware to limit the use of the IP block to these types of hardware. In addition, in addition to or instead, the DRM data of the license may define limiting data indicating license limits based on other variables that may be measured by sensors of the device. For example, the DRM data may define: a temperature limit of the license, for example based on an ambient temperature sensor; a voltage limit of the license, for example based on the level of a supply voltage in the circuit; a bandwidth limit of the license; a speed limit of the license, for example based on the reading of a GPS (global positioning system) of the device; an acceleration limit of the license, based for example on the reading of an accelerometer of the device; a humidity limit of the license, for example on the basis of an ambient humidity sensor of the device; a license light limit, for example based on an ambient light sensor of the device; a magnetic field limit of the license, for example based on a measurement of a Hall effect sensor of the device; a radioactivity limit of the license, for example on the basis of a measurement of a Geiger counter of the device; and / or another type of limit based on a measurement made by an appropriate sensor.
    In some embodiments, the DRM data modifies the verification code. For example, in some embodiments, the verification code includes the activation code, and some bits of the activation code are not provided or are incorrect, so that only a portion of the IP block is activated by the code activation. In other embodiments, other techniques that are not based on bit-by-bit activation / deactivation of the IP block may be used.
    Fig. 1B illustrates the license generator 116 in more detail according to an exemplary embodiment. The license generator 116 includes, for example, a key deduction function block (KDF1) 122, which generates a device key DK based on the device identifier provided by the integrated circuit. The license generator 116 also includes, for example, a cryptographic circuit 124, which applies the device key to the code or the verification codes of the IP blocks to be activated, in order to generate the license. For example, the cryptographic circuit 124 encodes the verification code (s) based on the device key by applying an encryption algorithm such as DES (Data Encryption Standard), AES (Advanced Encryption Standard), or the like algorithm. . DRM data can also be encrypted and be part of the license. In addition, in an embodiment described below in connection with FIG. 6, an IP key is also provided to the license generator 116 and encrypted by the circuit 124 to be included in the license.
    In some embodiments, rather than the license being generated by the IP vendor, the license is generated by the TTP, for example in the form of a SaaS (software as a service) solution. Thus, the TTP includes the license generator 116, which for example receives the device identifier, and the verification code (s) from the IP vendor, and in some cases the IP key. As represented by block 128 (CRYPTO), in some embodiments, the verification code (s) may be encrypted by the IP vendor using an IP vendor key (IP SELLER KEY), and the key of IP seller is also for example stored by the IP vendor in the IP block, which decrypts the verification code or codes. In this way, even the TTP can not access the verification codes. The license generation operation allows the TTP or IP vendor to count the number of integrated circuits to which licenses have been granted. In the case where each license is valid for a single integrated circuit, the number of licenses generated will be equal to the number of integrated circuits including protected IP blocks, and so an account can be made for the purpose of calculating the royalties due to the seller. IP, or detect a breach under the terms of a license agreement.
    The generated license is then provided to the integrated circuit 102, for example to the license server 114, which decrypts the license based on the device identifier of the integrated circuit 102, and extracts the verification code. For example, a symmetric encryption / decryption algorithm is used to encrypt the verification code by the license generator 116 using the device key, and then to decrypt the license at the integrated circuit 102, so that if the keys are identical , the verification code will be recovered successfully.
    Alternatively, rather than using symmetric encryption or decryption, asymmetric encryption or decryption can be achieved based on two keys. In such a case, the license server 114 derives for example a public key based on the device identifier, and the public key is provided, along with the device identifier, to the license generator 116. Rather than use a key deduction function 122 to generate a device key, the license generator 116 for example encrypts the license based on the public key. The license server 114 then receives for example the encrypted license from the license generator 116, and generates, on the basis of the identifier of the device, a private key to form the device key to decrypt the license.
    In yet another alternative, other types of encryption / decryption schemes may be used by any of the cryptographic blocks described herein, including the use of elliptic curve based algorithms.
    FIG. 2 schematically illustrates license components of the integrated circuit 102 of FIG. 1A in greater detail according to an exemplary embodiment, in the case where the communication between the license server 114 and the IPs 103 is based on a client-server configuration . However, in alternative embodiments, other types of communication configurations would be possible, such as a network on chip (NoC), or a multicast or broadcast protocol. The communication between the license server 114 and the IP 103 is for example secured using encryption.
    As illustrated in FIG. 2, a JT AG interface (Joined Test Action Group) is for example used to transmit the license received from the license generator 116 to a LICENSE MEMORY 202 of the integrated circuit 102. Of course, it would be possible to use other standard interfaces, such as the USB interface (universal serial bus).
    The memory 202 is for example a RAM (random access memory). The license memory 202 is internally coupled to the license server 114. The license server 114 communicates, for example, via a license bus (LICENSE BUS) 204, with the protected IP blocks 206. In In the example of FIG. 2, the license bus 204 is coupled to a client license circuit (LICENSE CLIENT) 208 associated with each IP block 206, which is itself coupled to the rest of the IP block 206, denoted IP core (IP CORE) 210 in FIG. 2. In the example of FIG. 2, there are N nuclei IP 1 to N, where N is for example an integer greater than or equal to 2.
    The license client 208 of each IP block 206, for example, checks the license, and on the basis of this verification, provides the activation code to the corresponding IP core in order to activate its functionalities. For example, each license client 208 includes an activation code register 212 in which the activation code is loaded if the license is found valid. The register 212 of each license client is coupled to the corresponding IP core 210 to activate its features.
    FIGS. 3A and 3B illustrate circuit examples used to make the activation of the IP blocks dependent on one or more bits of an activation code, by inserting logic gates in a signal path of the IP block.
    In the example of FIG. 3A, a circuit portion of the IP block represented by the cloud 302 provides an output signal on a line 304, which is coupled to the input of a synchronous logic device (A) 306. to make the activation of the output line 304 dependent on an activation bit, an activation circuit 308 is inserted between the output line 304 and the input of the synchronous device 306. The circuit 308 comprises, for example, an inverter (NOT) 310 having its input coupled to the line 304, and its output coupled to an input of an EXCLUSIVE OR (XOR) gate 312. The other input of the EXCLUSIVE OR gate 312 receives an activation bit en_a, which should be high to allow the data signal on line 304 to propagate to synchronous device 306.
    FIG. 3B illustrates another example of an activation circuit 318 inserted in the same signal path as in the example of FIG. 3A. This time, the circuit 318 includes an EXCLUSIVE OR (XOR) gate 320 having an input coupled to the line 304, and its other input coupled to receive an en_b activation bit. In this example, the enable bit should be low to allow the signal on line 304 to be propagated to the input of the synchronous device (B) 306.
    Thus, FIGS. 3A and 3B illustrate examples of circuits that can be inserted to activate circuit portions of IP blocks based on high and low activation bits respectively. Similar circuits can be inserted at various points in the IP block, so that the IP block will not operate without the correct activation code. Of course, Figures 3A and 3B are just a few examples of the logic gates that can be used to protect the IP block, and many different logic functions could be implemented based on the same principles. In some embodiments, the insertion is performed randomly, so that the activation code is a random value and does not depend on the function of the underlying circuit. In alternative embodiments, the insertion could be nonrandom. In addition, although in the examples of FIGS. 3Δ and 3B the circuit 308 is used in the case of the activation by a "1" bit of the activation code, and the circuit 318 is used in the case of the activation by a bit at "0" of the activation code, in alternative embodiments there are multiple different circuits which are used in the case of a bit activation at "1" and "0", and the selection between these circuits is random.
    Figure 4 schematically illustrates the license client 208 and the license server 114 of Figure 2 in more detail according to an exemplary embodiment.
    The license client 208 includes the activation register (ACTIVATION REGISTER) 212, which propagates an activation code to activation circuits (not shown in FIG. 4) of the IP core 210, via a bus activation (BUS ACTIVATION) 404.
    In the example of FIG. 4, the activation code (ACTIVATION CODE [ROM]) is stored in a memory 405 of the license client 208, which is for example a ROM (read only memory), and is only loaded in the activation register 212 when the loading signal LOAD is activated on a line 406. The loading signal is for example activated only after a successful verification of the verification code received via the license server 114.
    In one embodiment, the verification code extracted from the license by the license server 114 includes the activation code. In this case, to check the license by the license client 208, the activation code stored in the memory 405 is for example used to deduce a key for encrypting an interrogation signal transmitted to the license server 114, and to decrypt the answer. In particular, the activation code is transmitted to a key deduction function block (KDF2) 408, which generates an IP key (IP KEY) based on the activation code. A cryptographic block (CRYPTO) 410, which for example applies an encryption / decryption AES algorithm, encrypts a query value (CHALLENGE) 412, which is for example generated by a random number generator (RNG) 414. In one embodiment, RNG 414 is a true random number generator, or a pseudorandom number generator (PRNG). The encrypted interrogation value is transmitted to the license server 114 via the license bus 204.
    At the license server 114, a cryptographic circuit (CRYPTO) 416 for example applies the same algorithm as the block 410 to decrypt the query based on an IP key deduced from the activation code received with the license. In particular, the cryptographic block 416 receives the IP key (IP KEY) from a deduction function block (KDF2) 418, which in turn receives the activation code extracted from the license stored in the license memory 202. The activation code is extracted by a cryptographic circuit (CRYPTO) 420, which decrypts the license based on a device key (DEVICE KEY) provided by a key deduction function block 422 (KDF1). The KDF1 block 422 receives the device identifier from a circuit (DEVICE ID) 423, which for example generates and provides the on-demand device identifier from the KDF block 422, or which is a memory storing the identifier. of device. The key deduction function applied by block 422 is for example the same as that applied by block 122 of FIG. 1B, so that the device key is the same. Alternatively, as previously mentioned, the key deduction function applied by block 422 may generate public and private keys, the private key being used as a device key to decrypt the license.
    The key deduction function KDF1 applied by the blocks 122 and 422, and the key deduction function KDF2 applied by the blocks 408 and 418 are, for example, secret cryptographic functions to deduce the device key and the IP key in a secure manner. . In some embodiments, key deduction functions could be based on another key stored by blocks 122, 422 and / or 408, 418.
    A response circuit (RESPONSE) 424 for example receives the interrogation value decrypted by the block 416, and generates a response. For example, the response is a simple operation such as adding the value one to the query, or performing a polling permutation, or a more complex operation. In addition, the response may include DRM data extracted from the license by the cryptographic block 420.
    The response is encrypted by the cryptographic block 416, based again on the IP key, and returned to the cryptographic block 410 on the license bus 204 for decryption by the cryptographic block 410. In the license client 208, the response is supplied to a license client 208 CHECKER circuit 426 which verifies that the response corresponds to an accepted deduction from the interrogation. If the response is found to be valid, the load signal is enabled on line 406 so that the activation register 212 loads the activation code from the ROM 404.
    Further, in the case where the response includes DRM data extracted from the license, the tester for example stores the DRM data in a memory 428 and / or provides the DRM data for the IP core 210. The DRM data can limit activation to a certain type of circuit, such as ASICs, FPGAs etc. In addition or instead, the DRM data for example sets a time limit and / or a geographical limit for the activation of the IP block. For example, if a geographic boundary is applied, the DRM data defines for example an area in which the IP block can be activated, and position data, provided by a location device, such as a GPS (Global Positioning System) device. in the device 102, are used to check whether the device remains in the authorized zone. In the case where the DRM data indicate that the license has a limited validity period, the verifier 426 for example activates a timer, implemented for example by using a counter, to check when the limited validity period of the license expires. When this period expires, the tester 426 for example disables the load signal so that the enable register 212 is reset, and the IP block is deactivated again. Alternatively, the DRM information may be incorporated directly into the portion of the verification code provided in the response, so that only a portion of the activation code is loaded into the activation register, and thus unlocked. that part of the IP circuit.
    In another embodiment, the verification code extracted from the license does not include the activation code. In this case, the license client 208 comprises for example another memory (not shown), which is for example a ROM, and stores the verification code. This code is used to determine the IP key provided to the cryptographic circuit 410. The previously described method is then used to check the verification code, and if the verification is successful, the activation code stored in the memory 405 is loaded into the memory. activation register 212.
    Rather than using the key deduction function circuit 418 to determine the IP key, it can be transmitted with the license. Indeed, as described in connection with Figure IB, the license generator 116 can integrate the IP key in the license.
    Fig. 5 is a flowchart illustrating operations in a method, based on the circuit of Fig. 4, to activate an IP block using a license.
    In an operation 501, the license is received by the license server 114.
    In subsequent operations 502 to 504, the license is for example verified. These operations are for example performed at the time of putting into operation of the circuit, for example every time the circuit is powered. The license is available in the license memory 202. For example, the license is requested from an external source and loaded into the license memory 202 each time the device is powered on. Alternatively, the license memory 202 may be a non-volatile memory storing the license even when the device is turned off.
    In operation 502, the device key is derived from the device identifier, which is for example a PUF value.
    In operation 503, the license is decrypted using the device key to retrieve the verification code.
    In the operation 504, the verification code is verified by the IP license client 208, for example using a query / response protocol as previously described, and the activation code is loaded from the ROM 404 into the register. activation 212 to activate the IP block.
    An advantage of the implementation of Figure 4 is that the activation code is not transmitted on the license bus 204, which means that messages fraudulently intercepted on this bus can not be used to obtain the activation code.
    FIG. 6 schematically illustrates the license client 208 and the license server 114 of FIG. 2 in more detail according to an alternative embodiment with respect to the embodiment of FIG. 4. The elements of FIG. 6 which are identical or similar those in Figure 4 have the same numerical references and will not be described again in detail.
    In the embodiment of Figure 6, the activation code is not stored in a memory by the license client 208. Instead, the license client stores an IP key (KEY) in a memory 602, which is for example a ROM. This is for example the same IP key as that provided to the cryptographic block 124 of the license generator 116 of FIG. As in the embodiment of FIG. 4, the IP key is used by the cryptographic circuit 410 to encrypt an interrogation value provided by a block 412.
    In the license server 114, the IP key is extracted from the license received by the cryptographic block 420, and used by the cryptographic block 416 to decrypt the interrogation value. In the embodiment of FIG. 6, a response message transmitted to the license client 208 includes, for example, the response to the interrogation, and also the verification code, which is extracted by the cryptographic block 420 as in the Figure 4. The response message may also include the DRM data. The response message is encrypted by the cryptographic block 416 based on the IP key.
    In the license client 208, the cryptographic block 410 then decrypts the response message, and provides the response to the interrogation, the verification code, and the DRM data if any, to the verifier circuit 426. The circuit verifier 426 verifies that the interrogation value has been correctly modified by the response circuit 424, and passes the DRM data and the verification code to a DRM circuit 604, which for example operates similarly to the DRM circuit 428 of FIG. 4.
    The verification code comprises, for example, the activation code, in which case the activation code is then loaded directly into the activation register 212. In a variant, the verification code corresponds to the activation code encrypted by a key of IP seller. In this case, the IP vendor key is for example stored in another memory (not shown) of the license client 208, and is used by the cryptographic circuit 410 to decrypt the verification code and extract the activation code, which can then be loaded into the activation register 212.
    Fig. 7 is a flowchart illustrating operations in a method, based on the circuit of Fig. 6, for activating an IP block using a license.
    In an operation 701, the license is received by the license server 114.
    In subsequent operations 702 to 704, the license is for example verified. These operations are for example performed at the time of putting into operation of the circuit, for example every time the device is powered. The license is available in the license memory 202. For example, the license is requested from an external source and loaded into the license memory 202 each time the device is powered on. Alternatively, the license memory 202 may be a non-volatile memory storing the license even when the device is turned off.
    In operation 702, the device key is derived from the device identifier, which is for example a PUF value.
    In operation 703, the license is decrypted using the device key to retrieve the activation code.
    In operation 704, the activation code is received by the license client 206, and if the IP key received with the license is correct, the activation code is transmitted to the activation register 112 in order to activate the activation code. IP block.
    An advantage of the implementation of Figure 6 is that the activation code is not stored in a ROM, and so even if the IP key is obtained fraudulently, the protected IP block can not be activated.
    While in the embodiments of FIGS. 4 and 6, cryptographic circuits 410, 416 are used to add security to the license bus 204, in alternative embodiments, any system that ensures the security of the data transferred between the server of the server and the server. 114 licenses and the 208 license circuit could be used. For example, a hash or signature function could be used, as will now be described with reference to FIG.
    FIG. 8 schematically illustrates portions of the license server 114 and the license client 208 for communicating on the license bus 204 according to an exemplary embodiment, and for example which replace the KDF circuit 408, the cryptographic blocks 410, 416, and the interrogation, response and verification circuits 412, 424 and 426 of FIGS. 4 and 6. This example assumes that the verification code is stored by the license client 208, and is therefore not transmitted on the bus 204.
    An interrogation circuit (CHALLENGE) 802 generates, for example, an interrogation value, which is for example a numerical value based on a random value generated by a true random number generator (not illustrated in FIG. 8). The interrogation value is supplied to a response circuit (RESPONSE) 804, which generates a response to the interrogation, based on the verification code (CHECK CODE) stored in a memory 805, which is for example. a ROM. The response is for example generated by applying a function to the query value and the verification code, such as an addition or multiplication. The response value is then provided to a hash calculation circuit (HASH) 806, which generates a hash value based on the response. In some embodiments, the signature generated by the hash function is a MAC signature (message authentication code). The output of the hash circuit 806 is provided to a checker circuit (CHECKER) 808.
    The interrogation value generated by the interrogation circuit 802 is also transmitted on the license bus 204 to the license server 114, for example to a response circuit (RESPONSE) 810 of the license server 114. The response circuit 810 generates the response using the same algorithm as the circuit 802, but based on the verification code 811 extracted from the license. The response is then provided to a hash circuit (HASH) 812, which applies the same algorithm as the hash circuit 806, and transmits the result to the verifier circuit 808 for comparison with the value generated by the hash circuit 806. If the verification code 811 received with the license matches the verification code stored in the memory 805, the verification is successful, and the activation code is loaded into the activation register 212 (not shown in Figure 8).
    The embodiment of Figure 8 is merely an example. In alternative embodiments, the verification code is not used to modify the response 810, and instead the verification code is communicated to the license client 208 in a separate step. In such a case, the license client 208 for example does not store the verification code.
    In the embodiments of Figures 4, 6 and 8, the device identifier is for example read and used to verify a license securely, to prevent an attacker from forcing the same value as the device identifier to be used. For example, the license server 114 is adapted to read the identifier (DEVICE ID) associated with the integrated circuit on an interface protected by encryption. For example, the reading of the device identifier is based on an interrogation / response system similar to that implemented by the blocks 410, 412, 414, 416 and 424 in FIG. 4, or by the blocks 802, 804 , 806, 808, 810 and 812 in FIG.
    While in the example of Figure 2 the license client is part of each IP block, in alternative embodiments the license client associated with each IP block can be part of a centralized licensing system, as we will describe now with reference to Figure 9.
    FIG. 9 illustrates a centralized licensing system 900 comprising the license server 114, and the license clients (LICENSE CLIENT # 1 to #N) associated with each IP core 210. Activation buses 902 are provided between each client of the client. license and each IP kernel to transmit the activation code. Thus, the license verification functions are provided by a subdomain independent of the circuit, and this circuit 900 has for example a specific internal bus, a clock that can be separated from the IP blocks, and / or a dedicated memory for storing the data. licenses.
    Rather than the license server / client approach described so far, many alternative approaches could be used, including a NoC approach. A distributed approach using a serial bus could also be applied, as will now be described with reference to FIG.
    FIG. 10 illustrates a license system 1000 in which each IP block 206 comprises the IP core corresponding to N, and a license circuit 1002. The license circuits 1002 are for example coupled to a serial bus 1004 for provide data, and a serial bus 1006 to input data. A circulator (CIRCULATOR) 1007 for example inputs data into the bus 1004 from an input port of the integrated circuit and provides data from the bus 1006 to an output port of the integrated circuit.
    For example, each license circuit 1002 generates and stores its own device identifier (device ID1 to IDN device), which is part of the global device identifier. In addition, in some embodiments, another LICENSE CIRCUIT 1008 not directly associated with an IP block generates another DEVICE IDX device identifier. The global device identifier of the integrated circuit is for example equal to ID1 + ID2 + ... + IDN + IDX. The identifier IDX is for example provided in the case where the length of the ID1 to IDN combined identifiers is not long enough to provide a reliable unique identifier.
    Licenses LIC1 to LICN are for example introduced by the circulator 1007 in the bus 1006. Each license allows one of the blocks IP 206 to be activated. In particular, only the license encrypted by a key deduced from the device identifier of one of the IP blocks 206 can be decrypted by this IP block and used to activate the IP block.
    The licensing systems of FIGS. 2, 9 and 10 show, for example, the systems implemented on a given chip. In some cases, a circuit board may include several chips, each having one or more protected IP blocks.
    Fig. 11A illustrates an example of a map-level view 1100 of the licensing system. As illustrated, integrated circuits (CHIP 1, CHIP 2) 1102, 1104 each include, for example, a licensing system comprising a circuit for generating and / or storing a device identifier (DEVICE ID) and a DRM controller (DRM CONTROLLER). ) to selectively activate one or more protected circuits based on a license check. A memory (LICENSE CHIP1) is for example coupled to the circuit 1102 and stores a license associated with the integrated circuit 1102, and another memory (LICENSE CHIP2) is for example coupled to the integrated circuit 1104 and stores a license associated with the circuit 1104. In some Embodiments, the memories could be part of the same memory device.
    FIG. 11B illustrates a map-level view 1110 according to an alternative example with respect to that of FIG. 11A, in which a single memory 1112 stores one or more licenses (LICENSE) for all chips CHIP1, CHIP2, and so on. A DRM controller (DRM CONTROLER) 1114 for example communicates the license to each chip. In some embodiments, there is a different device identifier associated with each of the chips, and the device identifier (DEVICE ID) may include the combination of the device identifier of each chip, such as PUF (chipl) + PUF (chip2) + ... etc. Alternatively, a single device identifier could be used for all chips, chips CHIP1, CHIP2, etc. sharing the same device identifier.
    FIG. 12 illustrates a licensing system 1200 based on an FPGA 1202. The FPGA 1202 comprises for example a license loader circuit (LICENSE LOADER) 1204 to load a license, which is for example stored in a license memory (LICENSE MEMORY) 1206 of a configuration ROM (FPGA CONFIGURATION ROM) 1208. The configuration ROM is used to configure the FPGA when the device is turned on or after a reset. The FPGA also includes, for example, a LICENSE EMBEDDED MEMORY 1210 in which the license is loaded.
    With the description thus made of at least one illustrative embodiment, various alterations, modifications, and improvements will readily occur to those skilled in the art.
    For example, it will be readily apparent to those skilled in the art that the symmetric encryption / decryption implementations described herein could instead use asymmetric encryption / decryption.
    In addition, it will be apparent to those skilled in the art that the various elements described in connection with the various embodiments could be combined, in alternative embodiments, in any combination.
    权利要求:
    Claims (17)
    [1" id="c-fr-0001]
    A license verification circuit for selectively activating one or more protected circuits (206) of a device (102), the license verification circuit being adapted to: derive a device key (DEVICE KEY) from a identifier (DEVICE ID) associated with the device (102); receive a first license; decrypting the first license using the device key to retrieve a first verification code; activate a first protected circuit by loading an activation code into an activation register (212) associated with the first protected circuit on the basis of a verification of the first verification code.
    [2" id="c-fr-0002]
    A license verification circuit according to claim 1, wherein the identifier (DEVICE ID) associated with the device (102) is provided to a physically unclonable function, PUF.
    [3" id="c-fr-0003]
    A license verification circuit according to claim 1 or 2, wherein the license verification circuit is adapted to read the DEVICE ID associated with the device on an encrypted protected interface.
    [4" id="c-fr-0004]
    A license verification circuit according to any one of claims 1 to 3, comprising: a license server (114) comprising a key deduction circuit (422) for deriving the device key and a decryption circuit (420); ) to decipher the first license; a first license client (208) associated with the first protected circuit and including a first control circuit (426) for activating the first protected circuit based on the first verification code; and a second license client (208) associated with a second protected circuit and including a second control circuit (426) adapted to activate the second protected circuit by loading a second activation code into an activation register (212) associated with the second protected circuit.
    [5" id="c-fr-0005]
    A license verification circuit according to claim 4, wherein the license server (114) is adapted to transmit the first verification code to the first license client (208) and the second verification code to the second license client ( 208).
    [6" id="c-fr-0006]
    A license verification circuit according to claim 4 or 5, wherein the first verification code is encrypted by the license server (114) on the basis of another key (IP KEY) extracted from the first license and transmitted to the first control circuit (426) of the first license client (208).
    [7" id="c-fr-0007]
    The license verification circuit of claim 6, wherein the decryption circuit (420) is further adapted to extract the other key (IP KEY) from the first license.
    [8" id="c-fr-0008]
    The license verification circuit according to any one of claims 1 to 7, wherein the first verification code comprises the encrypted activation code using an IP vendor key, the first license client (208) being in possession. further adapted to store the IP vendor key in a memory and to decrypt the first verification code based on the IP vendor key to retrieve the activation code.
    [9" id="c-fr-0009]
    A license verification circuit according to claim 4, wherein the first license client (208) comprises: an interrogation generating circuit (802) comprising a random number generator (RNG) adapted to generate a value of polling and transmitting the query value to the license server (114); and a first response generation circuit (804, 806) adapted to generate a first response value based on at least the interrogation value, the license server (114) comprising: a second response generation circuit (810, 812) adapted to receive the interrogation value and to generate a second response value based on at least the interrogation value, the first license client further comprising a verification circuit adapted to compare a first response value to the second response value.
    [10" id="c-fr-0010]
    The license verification circuit of claim 9, wherein the first and second response generation circuits (804, 806, 810, 812) are adapted to generate the first and second response values based on a function. hash.
    [11" id="c-fr-0011]
    The license verification circuit of claims 4, 9 or 10, wherein the first license client (208) comprises a non-volatile memory (404) storing a copy of the activation code, the first control circuit (426). being adapted to load the copy of the activation code into the activation register (212) based on a verification of one or more values of the first verification code.
    [12" id="c-fr-0012]
    A license verification circuit according to any one of claims 1 to 11, wherein the verification code comprises other data (DRM) indicating one or more of the following: a period of validity of the license; a geographical limit of the license; a limitation of the license to one or more types of equipment; a temperature limitation of the license; a voltage limitation of the license; bandwidth limitation of the license; a speed limitation of the license; an acceleration limitation of the license; a humidity limitation of the license; a light level limitation of the license; . a magnetic field limitation of the license; and a radioactivity limitation of the license.
    [13" id="c-fr-0013]
    The license verification circuit of any one of claims 1 to 12, wherein the first activation code comprises a plurality of bits, and the first protected circuit comprises a plurality of logic gates adapted to selectively activate a path of signal of the first protected circuit, each logic gate having a first input coupled to a node of the first protected circuit and a second input coupled to receive one of the bits stored by the activation register (212).
    [14" id="c-fr-0014]
    A license verification system comprising: a first IP (proprietary) module (206) comprising a license verification circuit according to claim 1; a second IP module (206) comprising a license verification circuit according to claim 1; and a circulator (1007) adapted to transmit the first license to the first IP module and a second license to the second IP module.
    [15" id="c-fr-0015]
    A license generation circuit comprising: a key deduction circuit (122) adapted to derive a device key (DEVICE KEY) based on a device identifier (DEVICE ID) of a device (102); and an encryption circuit (124) adapted to generate a first license for one or more protected circuits of the device (102) by encrypting one or more activation codes using the device key.
    [16" id="c-fr-0016]
    The license generating circuit of claim 15, wherein the encryption circuit (124) is further adapted to encrypt another key (IP KEY) to be included in the first license.
    [17" id="c-fr-0017]
    A license verification method for selectively activating one or more protected circuits (206) of a device (102), the method comprising: deriving a device key (DEVICE KEY) from an identifier (DEVICE ID) associated with the device ; receive a first license; decrypting the first license using the device key to retrieve a first verification code; and activating a first protected circuit by loading the first activation code into an activation register (212) associated with the first protected circuit based on a verification of the first verification code.
    类似技术:
    公开号 | 公开日 | 专利标题
    EP3320471B1|2021-10-20|System and method for hardware ip modules authentication and licensing
    US8290150B2|2012-10-16|Method and system for electronically securing an electronic device using physically unclonable functions
    FR3101167A1|2021-03-26|METHOD OF USING A DEVICE FOR UNLOCKING ANOTHER DEVICE
    ES2318302T3|2009-05-01|EXECUTION TEST THAT USES RANDOM FUNCTION.
    FR2995707A1|2014-03-21|SYSTEMS AND METHODS FOR MANAGING ENCRYPTION KEYS IN A SECURE MICROCONTROLLER
    US20110002461A1|2011-01-06|Method and System for Electronically Securing an Electronic Biometric Device Using Physically Unclonable Functions
    CN111342963A|2020-06-26|Data uplink method, data storage method and device
    FR2806858A1|2001-09-28|CRYPTOGRAPHIC PROTECTION AGAINST FRAUD
    WO2019110945A1|2019-06-13|System and method for licensing and for measuring use of an ip block
    EP2919412A1|2015-09-16|Method and system for encrypting/decrypting data with a remote key and prior token verification
    EP2336931B1|2013-01-09|Method for signature verification
    Adi et al.2006|VLSI design exchange with intellectual property protection in FPGA environment using both secret and public-key cryptography
    EP3965361A1|2022-03-09|Data exchange between a client and a remote device, for example a secure module
    US20210357514A1|2021-11-18|System and device for data management
    Durai et al.2017|Real Time Implementation of QFT-PUF Architecture for Data Secure System-on-Chip
    EP1850259A2|2007-10-31|Method of protecting executable code and data of a computer system
    FR3060807A1|2018-06-22|METHOD OF VERIFYING THE INTEGRITY OF A PROGRAM, ELECTRONIC ENTITY AND ELECTRONIC APPARATUS COMPRISING SUCH AN ELECTRONIC ENTITY
    FR3098613A1|2021-01-15|PROCESS FOR MANAGING THE OPERATION OF AT LEAST ONE NUMBER APPLICATION SOFTWARE AND CORRESPONDING INTEGRATED CIRCUIT
    WO2021110518A1|2021-06-10|Method for cogenerating a shared cryptographic material, devices, system and corresponding computer program
    CH716291A2|2020-12-15|Decentralized signature process, under biometric control, of a transaction intended for a blockchain.
    CH716294A2|2020-12-15|Decentralized signature process, under biometric control and under conditions of personal identification and geolocation, of a transaction intended for a blockchain.
    FR2985337A1|2013-07-05|Method for securing result of cryptographic calculations against attack by injection of faults in chip card in electronic component, involves providing discretionary value processed by processing unit for one of output values of blocks
    FR3041841A1|2017-03-31|METHOD AND DEVICE FOR ACCESSING A RESOURCE USING A NUMBERED TOKEN
    FR2988197A1|2013-09-20|GENERATION AND IDENTITY VERIFICATION METHOD WITH THE UNICITY OF A CARRIER-OBJECT COUPLE
    同族专利:
    公开号 | 公开日
    JP2018523439A|2018-08-16|
    WO2017006058A1|2017-01-12|
    US20180196965A1|2018-07-12|
    EP3320471A1|2018-05-16|
    EP3320471B1|2021-10-20|
    KR20180048592A|2018-05-10|
    JP6854285B2|2021-04-07|
    US11023621B2|2021-06-01|
    FR3038757B1|2017-08-11|
    引用文献:
    公开号 | 申请日 | 公开日 | 申请人 | 专利标题
    US20110113392A1|2009-11-09|2011-05-12|Rajat Subhra Chakraborty|Protection of intellectual property cores through a design flow|
    EP0583709B1|1992-08-17|1999-05-06|THOMSON multimedia|Unforgeable identification device, identification device reader and method of identification|
    US5434917A|1993-10-13|1995-07-18|Thomson Consumer Electronics S.A.|Unforgeable identification device, identification device reader and method of identification|
    US6904527B1|2000-03-14|2005-06-07|Xilinx, Inc.|Intellectual property protection in a programmable logic device|
    JP2004021394A|2002-06-13|2004-01-22|Ricoh Co Ltd|Information processing system|
    US20100284539A1|2009-03-09|2010-11-11|The Regents Of The University Of Michigan|Methods for Protecting Against Piracy of Integrated Circuits|
    US8732468B2|2009-03-09|2014-05-20|The Regents Of The University Of Michigan|Protecting hardware circuit design by secret sharing|
    TWI419535B|2009-11-10|2013-12-11|Univ Nat Taiwan|Ip protection and control method thereof|
    US10771448B2|2012-08-10|2020-09-08|Cryptography Research, Inc.|Secure feature and key management in integrated circuits|
    US9742563B2|2012-09-28|2017-08-22|Intel Corporation|Secure provisioning of secret keys during integrated circuit manufacturing|
    US8938792B2|2012-12-28|2015-01-20|Intel Corporation|Device authentication using a physically unclonable functions based key generation system|
    US9071428B2|2013-03-15|2015-06-30|University Of Connecticut|Methods and systems for hardware piracy prevention|
    US9436848B2|2013-05-30|2016-09-06|Cryptography Research, Inc.|Configurator for secure feature and key manager|
    US9569601B2|2015-05-19|2017-02-14|Anvaya Solutions, Inc.|System and method for authenticating and enabling functioning of a manufactured electronic device|JP6922557B2|2017-08-29|2021-08-18|沖電気工業株式会社|Software management device and software management method program|
    FR3074933B1|2017-12-07|2021-05-21|Algodone|SYSTEM AND METHOD FOR LICENSE AND MEASUREMENT OF USE OF AN IP BLOCK|
    US10706179B2|2018-01-10|2020-07-07|General Electric Company|Secure provisioning of secrets into MPSoC devices using untrusted third-party systems|
    US10944557B2|2018-04-25|2021-03-09|Nxp B.V.|Secure activation of functionality in a data processing system|
    EP3620917B1|2018-09-06|2021-10-27|Siemens Aktiengesellschaft|Management of licences for soft ip on a partially reconfigurable hardware system|
    法律状态:
    2016-07-27| PLFP| Fee payment|Year of fee payment: 2 |
    2017-01-13| PLSC| Publication of the preliminary search report|Effective date: 20170113 |
    2017-07-28| PLFP| Fee payment|Year of fee payment: 3 |
    2018-07-04| PLFP| Fee payment|Year of fee payment: 4 |
    2018-10-12| CA| Change of address|Effective date: 20180910 |
    2018-10-12| TQ| Partial transmission of property|Owner name: CENTRE NATIONAL DE LA RECHERCHE SCIENTIFIQUE, FR Effective date: 20180910 Owner name: UNIVERSITE DE MONTPELLIER, FR Effective date: 20180910 |
    2019-07-23| PLFP| Fee payment|Year of fee payment: 5 |
    2020-07-28| PLFP| Fee payment|Year of fee payment: 6 |
    2021-09-13| PLFP| Fee payment|Year of fee payment: 7 |
    优先权:
    申请号 | 申请日 | 专利标题
    FR1556418A|FR3038757B1|2015-07-07|2015-07-07|SYSTEM AND METHOD FOR AUTHENTICATION AND IP LICENSE|FR1556418A| FR3038757B1|2015-07-07|2015-07-07|SYSTEM AND METHOD FOR AUTHENTICATION AND IP LICENSE|
    KR1020187002879A| KR20180048592A|2015-07-07|2016-07-06|Systems and methods for authentication and IP licensing of hardware modules|
    JP2018520030A| JP6854285B2|2015-07-07|2016-07-06|Device, license verification system, system and license verification method|
    PCT/FR2016/051718| WO2017006058A1|2015-07-07|2016-07-06|System and method for authenticating and ip licensing of hardware modules|
    US15/742,267| US11023621B2|2015-07-07|2016-07-06|System and method for authenticating and IP licensing of hardware modules|
    EP16750929.8A| EP3320471B1|2015-07-07|2016-07-06|System and method for hardware ip modules authentication and licensing|
    [返回顶部]